Integrated Chemical Microsensor Systems in CMOS Technology (Microtechnology and MEMS)

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Despite these efforts, the internal stresses in these layers remain considerably larger than what is required for robust planar suspended membranes with large areas. These problems are solved by depositing a stress-compensation layer on top, prior to the release of the beam by bulk-micromachining. Three different embodiments have been used to provide stress-compensation of the suspended membranes. The three embodiments of the invention are illustrated in FIGS. In the first embodiment of the invention, a superstrate [] 74 is bonded via an adhesive 78 to the area to be suspended.

The superstrate 74 can be any low-loss microwave material. In experiments, different types of glasses were used as a superstrate. The first samples of integrated multi-purpose power sensors were fabricated using this procedure.

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Stress compensation via bonding the superstrate [] 74 to an area to be suspended is not ideal since it does not lend itself to mass-fabrication. In many cases, special adhesives are used for bonding since the microwave properties of the component to be fabricated is important. This leads to investigation of the other two stress-compensation techniques.

The second embodiment of the invention is shown in FIG. A carefully deposited thin silicon nitride SiN layer 82 is placed on the suspended membrane 80 under tensile stress. Multiple coatings are necessary using the 1. A single thick layer [] 84 is screen-printed on the membrane area.

This is advantageous because compensation with thin SiN films requires a high-resolution mask to obtain electrical contacts. However, if the compensation is performed by screen-printing, then the film can be deposited on the membrane 80 area only. This eliminates the need for an additional high-resolution mask. The size of membranes needed for microwave purposes is usually large e.

Therefore, stress-compensation by screen-printing is more cost-effective compared to thin-film techniques. In this post-processing procedure, the use of thick film stress-compensation is advantageous. Particularly, it is necessary to have large cavities for the operation of some of the devices, such as tunable capacitors, switches and microfluidic components. A thick layer can perform various functions besides stress-compensating the large CMOS membranes required for microwave operation. For example, it can be used to fabricate reconfigurable microwave components by supporting an additional layer of metallization.

It is also possible to have high quality gold plated microfluidic structures supported by this layer to fabricate microfluidic devices or sensors. A polymide with the trade name Epo-tek , manufactured by Epoxy Technology, Inc. Increasing the film thickness caused curing problems.

Integrated Chemical Microsensor Systems in CMOS Technology Microtechnology and MEMS

If the recommended curing cycle e. The optimum thickness of the polyimide film varies with the application. Without any change in the curing procedure, a smooth, uniform, pin-hole and crack free polyamide films can be obtained on CMOS chips by applying multiple coats of polymide. Each coating is cured with the same procedure described above. Electrical properties of the polyimide changes with processing. Therefore, the curing procedure should be followed closely to obtain the same properties. An optimum fabrication should yield films with dielectric constants as low as 2.

Low dielectric constant films are desirable for low-dispersion microwave propagation. Table 2 provides a comparison between polymide and benzocyclobutene BCB. Polyimides are high temperature engineering polymers originally developed by the DuPont Company. When compared to most other organic or polymeric materials, polyimides exhibit an exceptional combination of thermal stability e.


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Because of their high degree of ductility and inherently low CTE, polyimides can be readily implemented into a variety of microelectronic applications. Polymides with the trade names DuPont Pyralin series and Epo-Tek are popular in stress-buffer coating of silicon wafers. There is another class of polymers derived for low-k microelectronics applications. They are particularly good for thin film applications such as interlayer insulators. Both of these materials are investigated because of their low dielectric constants, which is desired for microwave applications.

A brief comparison is included in Table 2.

The back side of the silicon layer [] 12 is patterned by using standard photolithographic techniques. Shipley positive photoresist is used in the back side patterning and in the front side protection during etching.

Integrated Chemical Microsensor Systems in CMOS Technology

Spinning speeds higher than rpm are used during the preparation of the samples. The polymide film 28 should be protected by using multilayer coating. A simple photolithographic preparation is good enough for bulk micromachining with xenon-difluoride XeF 2. If wet type of bulk micromachining is needed then appropriate protection should be provided for the necessary parts of the die. For example, silicon etching with tetramethylammonium hydroxide TMAH cannot be performed with a photoresist masking. Low temperature oxide should be used as a mask in TMAH.

It is also known that polyimide film reacts with TMAH solution, therefore, those regions with polyimide films should be well protected. XeF 2 pulse etching is very simple and highly selective for silicon. The drawback of this method is that it is isotropic and therefore it is harder to control the etching profile with the increased surface roughness during long etch cycles. Depending on the area and the volume of the exposed Si and the pulse parameters, back side etching might take from 30 minutes to a few hours of etching. This step of the process is illustrated in FIGS.

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During back side etching, all of the silicon underneath the compensated area is removed. This exposes the sacrificial photoresist which is the first thick film photo resist layer 46 and the electrical contact pads accessible from the back side of the MEMS IC At room temperature, XeF [] 2 has a sublimation pressure of about 4 Torr. The gas forms HF in the presence of water vapor.

Therefore, proper ventilation is necessary. The reaction between silicon and XeF 2 is given below:. The etch has very high selectivity to common thin films including silicon dioxide, silicon nitride, photoresist and aluminum. It consists of a two stage mechanical roughing pump, stainless steel or aluminum etching chamber, a capacitive pressure gauge, pneumatic valves a needle valve. All the pneumatic valves are controlled with a computer. The XeF [] 2 is metered by using a pressure to the etching chamber. Typical XeF 2 fill-in duration is less than 10 sec, but the time depends on the etching chamber.

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One of the systems used had a 4 inch wafer processing capability, thus a large etching chamber. The fill-in time for this chamber is more than 45 sec. It takes approximately of 2 Torr-pulses of XeF [] 2 to etch 4. Each pulse is sec long including the fill-in time. In this step, the sacrificial photoresist which is the first thick film photo resist layer [] 46 is removed through open holes in the CMOS membrane. One of the unique features of this process is that it allows the fabrication of various types of sensors and actuators.

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This step assures the integration of these low-frequency components. Arguably, this step might be the most important innovation brought to the fabrication process. Integration of chips at the system level and their packaging can no longer be considered independent from the low level fabrication outlined above. However, low electron mobility in silicon prevents the high frequency operation of active devices in this medium even the state of the art photolithographic technology is used.

On the other hand, by using silicon-germanium heterojunction bipolar transistor technology SiGe-HBT transistors with 90 GHz transit frequency f [] t and maximum oscillation frequency f max have been demonstrated. Although post-processing of these dies are also possible with proper choice of etchant systems, we believe that because of the cost considerations integration of such specialized chips with CM-MEMS fabricated chips are more cost-effective. Flip-chip integration of active microwave components have been studied as one of the most processing integration methods at high frequencies.

Based on these studies several systems have already been announced. The present process for fabricating a MEMS IC [] 10 can easily be altered to incorporate flip-chip integration of active devices. Most of the current techniques use electroplated gold bumps to bond two substrates together. Usually electroplating requires additional processing. Therefore, increase the cost of the fabrication. However, the proposed process already has the electroplating step. This eliminates the additional cost for integration.

Although it is not shown, the flip-chip integration of SiGe or GaAs based circuits can be done after stripping off the second thick film photo resist layer 54 and exposing the seed layer Necessary underfill must be carried out multiple times to fill the large air gap because of the exposed areas of the first thick film photo resist layer 46 underneath the integrated chip.

Similarly, other special chips can be integrated with the micromachined CMOS chip in similar manner. Specifically, the fabrication of a novel thermally actuated tunable capacitor 86 is described. The capacitor is designed by preferably using 1. The final layout of the tunable capacitor [] 86 is shown in FIG.


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  5. The fabricated devices include open holes 44 necessary to remove the sacrificial first thick film photo resist layer All the contact pads 88 shown in FIG. That is the contact pads 88 are accessible from both sides of the CMOS membrane 80 after the silicon etch process. Four low-resolution masks are used for post-processing as shown in FIG. Mask [] 90 shows a pattern for the first thick film photo resist layer 46 to be applied to the opening Mask 92 shows a pattern for the second thick film photo resist layer 52 for the electroplating portion of the MEMS IC 10 fabrication process.